Overview
Description
The 87339I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 87339I-11 has one differential clock input pair. The CLK, nCLK pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 87339I-11 ideal for clock distribution applications demanding well defined performance and repeatability.
Features
- Dual ÷2, ÷4 differential 3.3V LVPECL outputs
- Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
- One differential CLK, nCLK input pair
- CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Maximum clock input frequency: 1GHz
- Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
- Output skew: 35ps (maximum)
- Part-to-part skew: 385ps (maximum)
- Bank skew: Bank A - 20ps (maximum) Bank B - 20ps (maximum)
- Propagation delay: 2.1ns (maximum)
- LVPECL mode operating voltage supply range: VCC = 3V to 3.6V, VEE = 0V
- Available in lead-free (RoHS 6) package
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.