The 9SQ440 is an Intel CK440 main clock synthesizer for Intel cloud and HPC platforms, and newer Intel-based server platforms. 9SQ440 is a single-chip, PCIe Gen5 compliant, and is designed to work as a complete clock solution or in combination with DB2000Q-compliant clock buffers to provide point-to-point clocks to multiple receiving agents.

Features

  • PCIe Gen5 phase jitter < 53fs rms
  • 3 x 25MHz dedicated output pairs
  • 7 x 100MHz dedicated output pairs with individual OE# pins
  • 9 MXCLK output pairs multiplexable between 100MHz and 25MHz
  • 3.3V operation
  • 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 80 resistors, saving 130mm2 of area
  • 9 selectable SMBus addresses
  • Supports 0%, -0.3% and -0.5% spread-spectrum amounts
  • Side-Band Interface allows real-time hardware control of all output enables
  • OE# pin control of 100M[6:0] supports PCIe slot CLKREQ#
  • Dedicated Platform Time input and output clocks (PFT_IN and PFT_OUT)
  • 8 × 8 mm dual-row 100-VFQFPN
  • -40°C to +85°C operating temperature range

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9SQ440NQQI
Package Info
 Active VFQFPN 100 I Yes Tray
Availability

Buy / Quote
9SQ440NQQI8
Package Info
 Active VFQFPN 100 I Yes Reel
Availability
Buy / Quote

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9SQ440 Datasheet – Datasheet PDF 604 KB
Application Notes & White Papers
Crystal Layout and Routing Recommendations – Application Note PDF 78 KB
NQQ100 Package Solder Paste Stencil – Application Note PDF 115 KB
PCIe Reference Clock Jitter Measurements for Gen5 and Beyond – White Paper PDF 1.35 MB
AN-828 Termination - LVPECL – Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-838 Peak-to-Peak Jitter Calculations – Application Note PDF 115 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
Other
PCI Express Timing Solutions Overview – Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
QFN Mounting Manual 日本語, 简体中文 Other PDF 3.19 MB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Type Date
Future-proof Your PCIe® Designs Blog Post Oct 16, 2019
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 18, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 28, 2017
IDT Introduces Industry's Most Complete and Lowest-power Timing Solution for Intel's Romley Server Platform News Dec 14, 2011