9DML4493A is a Gen1–5 compliant 4-input, 4-output clock multiplexer. The device supports complex clock architectures like CC, SRIS and SRNS while providing very low additive jitter. This multiplexer supports standard industry signaling such as  LVPECL, LVDS, HCSL and LVCMOS. The 9DML4493 also features configurable strap pins, making it ideal for applications where serial bus such as I2C is not available.
 
For information regarding evaluation boards and material, please contact your local Renesas sales representative.
 

Features

  • PCIe Gen1–5 compliance
  • Pin selectable 4:4 mode or dual 2:2 MUX mode
  • Input frequency range: 1Hz to 350MHz
  • Supports LVPECL, LVDS, HCSL and LVCMOS input reference clocks
  • Configuration strap pin option selecting output impedance of 100Ω or 85Ω for board space optimization
  • Three pin-selectable output amplitudes per bank
  • Flexible power supply voltage of 1.8V, 2.5V, or 3.3V
  • -40°C to +85°C operating temperature range
  • 5 × 5 mm 32-VFQFPN package; small board footprint
  • Easy AC-coupling to other logic families. See application note AN-891.

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
9DML4493ANLGI
Active VFQFPN 32 I 85, 100 Tray
Availability
9DML4493ANLGI8
Active VFQFPN 32 I 85, 100 Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DML4493A Datasheet Datasheet PDF 447 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Downloads
9DML4493A IBIS Model Model - IBIS ZIP 149 KB
Other
PCI Express Timing Solutions Overview Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB