Overview
Description
Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for non parity DDR2 RDIMMs for 400 and 533MHz.
Features
- 1:1 and 1:2 registered buffer
- 1.8V Operation
- SSTL_18 style clock and data inputs
- Differential CLK input
- Control inputs compatible with LVCMOS levels
- Flow-through architecture for optimum PCB design
- Latch-up performance exceeds 100mA
- ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0)
- Maximum operating frequency: 340MHz
Comparison
Applications
Documentation
= Featured Documentation
Log in required to subscribe
|
|
|
---|---|---|
Type | Title | Date |
Datasheet | PDF 232 KB | |
End Of Life Notice | PDF 407 KB | |
End Of Life Notice | PDF 192 KB | |
Product Change Notice | PDF 252 KB | |
Product Change Notice | PDF 194 KB | |
Product Change Notice | PDF 729 KB | |
6 items
|
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.