CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A 1 signifies that the position's data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the 0 state and sees a 1 in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to 0. The first and last control flip-flops have buffered outputs. Since all empty locations bubble automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.


  • 4 Bits x 16 Words
  • High voltage type (20V rating)
  • Independent asynchronous inputs and outputs
  • 3-state outputs
  • Expandable in either direction
  • Status indicators on input and output
  • Reset capability
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • 5V, 10V and 15V parametric ratings
  • Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
  • Noise margin (over full package/temperature range) 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
  • Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"


  • Bit rate smoothing
  • CPU/Terminal buffering
  • Data communications
  • Peripheral buffering
  • Line printer input buffers
  • Auto dialers
  • CRT buffer memories
  • Radar data acquisition


Title language Type Format File Size Date
star CD40105BMS Datasheet Datasheet PDF 409 KB
AN9867: End of Life Derating: A Necessity or Overkill Application Note PDF 338 KB
Wafer by Wafer Low Dose Rate Acceptance White Paper White Paper PDF 533 KB
PA11003 - Packing Method Change for Intersil TO-xx Metal Can and Flat Pack Packaged Products Product Advisory PDF 499 KB
PCN10123 - Alternate Die Attach Material for Assembly of Intersil Hermetic Packaged Products - Intersil Palm Bay, FL. (ISP) Product Change Notice PDF 230 KB
Intersil Space Products Brochure Brochure PDF 3.16 MB
Intersil Commercial Lab Services Brochure PDF 364 KB
Standard Microcircuit Drawing 5962-96602 (CD40105BMS) Other 0 KB
PIN19011 - Price Increase for the Listed Renesas Electronics America (REA) Radiation Hardened Space Products Price Increase Notice PDF 360 KB

printNews & Additional Resources

Type Date Sort ascending
Low Dose Rate Acceptance Testing Page Mar 26, 2020
Standard Data Package Page Mar 20, 2020
Rad Hard SMD Test Flow Page Mar 20, 2020
Rad Hard Test Reports Page Mar 20, 2020