The 672-01/02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on IDT's proprietary low jitter Phase-Locked Loop (PLL) techniques, each device provides five low-skew outputs, with clock rates up to 84 MHz for the 672-01 and up to 135 MHz for the 672-02. By providing outputs delayed one quarter clock cycle, the device is useful for systems requiring early or late clocks. The 672-01/02 include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock FBCLK is tied to the FBIN pin. IDT manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world.


  • Packaged in 16-pin SOIC
  • Pb (lead) free package, RoHS compliant
  • Input clock range from 5 MHz to 150 MHz (depends multiplier)
  • Clock outputs from up to 84 MHz (672-01) and up 135 MHz (672-02)
  • Zero input-output delay
  • Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections
  • Four accurate (<250 ps) outputs with 0°, 90°, 180°, and 270° phase shift from ICLK, and one FBCLK (0°)
  • Separate supply for output clocks from 2.5 V to 5 V
  • Full CMOS outputs (TTL compatible)
  • Tri-state mode for board-level testing
  • Includes Power-down for power savings
  • Advanced, low power, sub-micron CMOS process
  • 3.3 V to 5 V operating voltage
  • Industrial temperature version available

Product Options

Orderable Part ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Not Recommended for New Designs SOIC 16 I Yes Tube
Not Recommended for New Designs SOIC 16 I Yes Reel
Obsolete SOIC 16 C Yes Tube
Obsolete SOIC 16 C Yes Reel

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
672-02 Datasheet Datasheet PDF 152 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
System Applications and Design Guidelines with IDT’s Zero-Delay Buffers Application Note PDF 294 KB
PDN# : CQ-18-03 Product Discontinuance Notice Product Discontinuation Notice PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB
672-02 5V IBIS Model Model - IBIS ZIP 3 KB
672-02 3.3V IBIS Model Model - IBIS ZIP 3 KB
672_3 Model - IBIS ZIP 3 KB
672_5 Model - IBIS ZIP 3 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB