Overview
Description
The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.
Features
- High system speed 4.5ns clock access time (117 MHz)
- Single-cycle deselect functionality (Compatible with
- Micron Part # MT58LC64K32D7LG-XX)
- LBO input selects interleaved or linear burst mode
- Self-timed write cycle with global write control (GW), byte
- write enable (BWE), and byte writes (BWx)
- Power down controlled by ZZ input
- Operates with a single 3.3V power supply (+10/-5%)
- Available in 100-pin TQFP package
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.