Overview
Description
The M2053 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.
Features
- Integrated SAW delay line
- Output of 15 to 700 MHz *
- Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz)
- Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios:
- - M2053: Map 10GbE to 66B/64B or 255/238 FEC
- Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance
- LVPECL clock output (CML and LVDS options available)
- Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
- Loss of Lock (LOL) output pin
- Narrow Bandwidth control input (NBW Pin)
- Hitless Switching (HS) options with or without Phase Build-out (PBO) available
- performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection
- Single 3.3V power supply
- Small 9 x 9 mm SMT (surface mount) package
Comparison
Applications
Documentation
Log in required to subscribe
|
|
|
---|---|---|
Type | Title | Date |
Product Change Notice | PDF 361 KB | |
End Of Life Notice | PDF 71 KB | |
2 items
|
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.