The 854S713I is a differential, high-speed 2:1 data/clock multiplexer and 1:2 clock/data demultiplexer in one device. The outputs support pre-emphasis in order to drive backplanes and long transmission lines while reducing inter-symbol interference effects. The pre-emphasis level is individually configurable to optimize for low bit error rate or power consumption. Pre-emphasis utilizes an increased output voltage swing for transition bits. The device is optimized for data rates up to 4.5Gbps (NRZ) and for deterministic jitter in data applications and low additive jitter in clock applications. The outputs are LVDS-compliant while the differential input is compatible with a variety of signal levels such as LVDS, LVPECL and CML. A small package (4.0mm x 4.0mm 24-lead VFQFN) supports space-efficient board designs. The 854S713I operates from a 3.3V power supply and supports the industrial temperature range of -40 to +85 deg C.


  • 2:1 differential data/clock multiplexer and 1:2 data/clock demultiplexer with a two-output fanout
  • 4.5 Gbps max. data rate (NRZ)
  • Differential LVDS outputs
  • Differential inputs supporting LVDS, LVPECL and CML levels
  • Configurable output pre-emphasis
  • Low-skew output: 25ps (maximum)
  • Low data deterministic jitter: 3ps (maximum)
  • LVCMOS interface levels for the control inputs
  • Additive phase jitter, RMS: 0.09ps (typical)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 24 I Yes Tray
Obsolete VFQFPN 24 I Yes Reel


Title language Type Format File Size Date
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB


Title language Type Format File Size Date
854S713I 3.3V IBIS Model Model - IBIS ZIP 60 KB