Overview

Description

The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.

Features

  • User selectable HSTL/LVTTL Input and/or Output
  • 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
  • 3.3V Input tolerant
  • Program programmable flags by either serial or parallel means
  • Big-Endian/Little-Endian user selectable byte representation
  • Auto power down minimizes standby power consumption
  • Master Reset clears entire FIFO
  • Partial Reset clears data, but retains programmable settings
  • Empty, Full and Half-Full flags signal FIFO status
  • Output enable puts data outputs into high impedance state
  • JTAG port, provided for Boundary Scan function
  • Available in 208-pin and 240-pin PBGA packages
  • Easily expandable in depth and width
  • Independent Read and Write Clocks (permit reading and writing simultaneously)
  • Industrial temperature range (–40C to +85C) is available

Documentation

Title Type Date
PDF367 KB
Datasheet
TXT14 KB
Application Note
PDF123 KB
Guide
PDF524 KB
Product Change Notice
PDF24 KB
Product Change Notice
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Product Change Notice
PDF729 KB
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PDF80 KB
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PDF38 KB
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Product Change Notice

Design & Development

Models

Models

Title Type Date
Model - BSDL
Model - IBIS
Model - SPICE

Support