RZ/V2MA Evaluation Board Kit
This product is an evaluation board with RZ/V2MA configured as the key device. The RZ/V2MA Evaluation Board Kit is configured with the main board, base board, and...
Overview
Description
The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1–4 applications with integrated output terminations providing Zo = 100Ω. The device has two output enables for clock management and supports two different spread spectrum levels in addition to spread off.
Features
- PCIe Gen 1–4 compliant
- Integrated terminations provide 100Ω differential Zo: reduced component count and board space
- 1.8V operation: reduced power consumption
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs are blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25%, or -0.5% spread on DIF outputs: reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface is not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 4mm x 4mm 24-pin VFQFPN; minimal board space
Comparison
Applications
Design & Development
Boards & Kits
Boards & Kits
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Processing table
| VFQFPN | 24 | I | Yes | Tray | 1 | Get Samples, | ||
| VFQFPN | 24 | I | Yes | Reel | 1 | 1.711 | ||
| VFQFPN | 24 | C | Yes | Tray | 1 | 1.555 | Get Samples, | |
| VFQFPN | 24 | C | Yes | Reel | 1 | 1.555 |
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- Document icon next to product name in row: View the featured document for this product
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- Cart icon to the right of the chip icon: Indicates that samples are available for this product
Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
News & Blog Posts
| Blog Post | Apr 14, 2022 | ||
| Blog Post | May 22, 2018 | ||
| News | Apr 30, 2018 |
