Overview
Description
The 72T36135M is a 512K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a wide extended x 36 bus to allow ample data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data at very high performance. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.
Features
- Functionally and pin compatible to 9Mbit 72T36125
- User selectable HSTL/LVTTL Input and/or Output
- User selectable Asynchronous read and/or write port timing
- Program programmable flags by either serial or parallel means
- Auto power down minimizes standby power consumption
- Master Reset clears entire FIFO
- Partial Reset clears data, but retains programmable settings
- Empty and Full flags signal FIFO status
- Output enable puts data outputs into high impedance state
- JTAG port, provided for Boundary Scan function
- Available in 240-pin PBGA package
- Independent Read and Write Clocks (permit reading and writing simultaneously)
- Industrial temperature range (–40C to +85C) is available
Comparison
Applications
Documentation
= Featured Documentation
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Type | Title | Date |
Datasheet | PDF 630 KB | |
End Of Life Notice | PDF 1.29 MB | |
Guide | PDF 123 KB | |
Product Change Notice | PDF 99 KB | |
Product Change Notice | PDF 729 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.