Overview

Description

The 524S is a low skew, single input to four output, LVCMOS clock buffer that offers a best-in-class additive phase jitter of sub 50fs.

Features

  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low-cost clock buffer
  • Packaged in an 8-SOIC and 8-DFN, Pb-free
  • ICLK is PDT and may be driven before VDD is applied
  • Direct-coupled signal path suitable for 1pps clocks
  • Input/Output clock frequency up to 200MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Advanced, low-power CMOS process
  • Extended temperature range: -40 °C to +105 °C

Comparison

Applications

Documentation

Type Title Date
Datasheet PDF 267 KB
Application Note PDF 187 KB
Overview PDF 217 KB
Product Change Notice PDF 268 KB
Product Change Notice PDF 611 KB
Product Change Notice PDF 611 KB
Application Note PDF 495 KB
Application Note PDF 442 KB
Application Note PDF 565 KB
9 items

Design & Development

Models

Videos & Training

Low-jitter LVCMOS Fanout Clock Buffers by IDT

This video overviews the LVCMOS Fanout Buffers, showcasing their best-in-class performance with extremely low phase jitter, minimal output skew, and low power consumption, along with other competitive features.