The 9ZXL0652E is a second-generation, enhanced-performance DB800ZL differential buffer. The part is functionally compatible to the 9ZXL0652A, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0652E has an SMBus Write Lockout pin for increased device and system security.
Features
- SMBus write lock feature; increases system security
- PCIe Gen 1–5 compliance
- LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save 48mm² of area
- 6 OE# pins; hardware control of each output
- Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz PLL Mode; UPI support
- 5 × 5 mm 40-VFQFPN package; small board footprint
