The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

Features

  • Integrated terminations provide 100Ω differential Zo; reduced component count and board space
  • 1.8V operation; reduced power consumption
  • OE# pins; support DIF power management
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space saving 5 x 5 mm 32-VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment

descriptionDocumentation

Title language Type Format File Size Date
Datasheets & Errata
star 9FGV0441 Datasheet – Datasheet PDF 580 KB
User Guides & Manuals
Timing Products for NXP (Freescale) i.MX 简体中文 Guide PDF 321 KB
Application Notes & White Papers
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-918 Programmable Clocks vs Crystal Oscillators – Application Note PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location – Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location – Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location – Product Change Notice PDF 544 KB
Other
PCI Express Timing Solutions Overview – Overview PDF 275 KB
IDT Clock Generation Overview – Overview PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

file_downloadDownloads

Title language Type Format File Size Date
Models
9FGV0441 IBIS Model – Model - IBIS ZIP 97 KB

printNews & Additional Resources

Type Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 22, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News May 1, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 19, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 29, 2017
IDT Announces World’s Lowest-power PCI Express Timing Family News Aug 16, 2012