概要

The 9FG830 is a Frequency Timing Generator that provides 8 HCSL differential output pairs. These outputs support PCI-Express Gen3, and QPI applications. The part supports Spread Spectrum and synthesizes several additional output frequencies from either a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock. The 9FG830 also outputs a copy of the reference clock. Complete control of the device is available via strapping pins or via the SMBus interface.

9FG830 - Block Diagram
9FG830 - Pinout
9FG830 - Block Diagram
9FG830 - Pinout
  • 8 - 0.7 V current mode differential HCSL output pairs
  • 1 - 3.3 V LVTTL REF output
  • Pin-to-Pin with 9FG108D
  • Easy upgrade to PCIe Gen3
  • Generates common frequencies from 14.318 MHz or 25 MHz; single part supports multiple applications
  • Provides copy of reference output; eliminates need for additional crystal or oscillator
  • Three spread spectrum modes: -0.5%, +/-0.25%, and off; EMI reduction
  • Unused outputs may be disabled in Hi-Z; save system power
  • Device may be configured by SMBus and/or strap pins; can be used in systems without SMBus
  • Cycle-to-cycle jitter: < 50 ps with 25 MHz input
  • Output-to-output skew: <50 ps
  • Phase jitter: PCIe Gen3 < 1 ps RMS
  • Phase jitter: QPI 9.6GB/s < 0.2 ps RMS
  • 10 ppm synthesis error with 25 MHz input and Spread Off

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9FG830AFILF
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 I Yes Tube
    9FG830AFILFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 I Yes Reel
    9FG830AFLF
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Tube
    9FG830AFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Reel
    9FG830AGILF
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 I Yes Tube
    9FG830AGILFT
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 I Yes Reel
    9FG830AGLF
    circle廃止品
    memory
    view_in_ar
    今すぐ購入する
    		TSSOP 48 C Yes Tube
    9FG830AGLFT
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 C Yes Reel
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    ビデオ&トレーニング

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview