The 8T49N240 has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with three integer and one fractional output dividers, allowing the generation of up to two different  output frequencies, ranging from 8kHz to 1GHz. Output frequencies can be completely independent of the input frequencies, two of these frequencies can be completely independent of each other and the other two will be integer-related to one of the other two frequencies. The four outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.

The 8T49N240 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or in test and measurement applications. For example, the 8T49N240 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications in order to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card. The 8T49N240 provides a 200fs (typical, 12kHz to 20MHz) RMS jitter performance that provides users with additional margin in their designs.

IDT’s third generation Universal Frequency Translator family also includes the 8T49N241 (2-in / 1-PLL / 4-out), 8T49N242 (2-in / 1-PLL / 4-out), the 8T49N285 (2-in / 1-PLL / 8-out), the 8T49N286 (4-in / 2-PLL / 8-out) and the 8T49N287 (2-in / 2-PLL / 8-out). These devices are complemented by the 82P33714 and 82P33731 synchronous equipment timing source (SETS) for Synchronous Ethernet (SyncE) and 10G-40G SyncE, respectively.

To see other devices in this product family, visit the Universal Frequency Translators page.


  • Compliant with the requirements outlined in Telcordia GR-253-CORE (SONET) & ITU-T G.813/G.8262 (SDH/SONET & SyncE) when paired with a Synchronous Equipment Timing Source (SETS ) device
  • Generates up to 4 LVPECL / LVDS / HCSL or 16 LVCMOS output clocks ranging from 8kHz up to 1.0GHz (diff), 8kHz to 250MHz (LVCMOS), that meet jitter limits for 10G up to 25G Ethernet applications
  • 0.2ps RMS (including spurs), 12kHz to 20MHz
  • Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input clocks ranging from 8kHz up to 875MHz
  • Auto and manual input clock selection with hitless switching
  • Clock input monitoring, including support for gapped clocks
  • Phase-Slope Limiting and Fully Hitless Switching options to control output phase transients
  • Operates from a 25MHz to 50MHz crystal
  • Register programmable through I²C or via external I²C EEPROM
  • 8T49N240-991 “Boot from EEPROM”
  • 8T49N240-994 “powers up disabled”
  • Supported by IDT Timing Commander Software™

Product Options

This device is factory-configurable. Try the Custom Part Configuration Utility.
Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Carrier Type Description Buy Sample
Active VFQFPN 40 I Tray Boot from EEPROM
Active VFQFPN 40 I Reel Boot from EEPROM
Active VFQFPN 40 I Tray Powers up disabled
Active VFQFPN 40 I Reel Powers up disabled


Title language Type Format File Size Date
Datasheets & Errata
8T49N240 Datasheet Datasheet PDF 1.80 MB
8T49N240-991 Datasheet Addendum Datasheet PDF 164 KB
8T49N240-994 Datasheet Addendum Datasheet PDF 153 KB
User Guides & Manuals
Timing Commander Installation Guide Guide PDF 497 KB
8T49N24x Evaluation Board User Guide Manual - Eval Board PDF 1.41 MB
FemtoNG Universal Frequency Translator Ordering Product Information Guide Manual - User Reference PDF 270 KB
Application Notes & White Papers
App Note 932 - Description for Startup and Calibration for UFT3G Family Application Note PDF 604 KB
8T49N24x EEPROM Programming Guide Application Note PDF 593 KB
8T49N24x Power-Up Configuration Guide Application Note PDF 175 KB
AN-828 Termination - LVPECL Application Note PDF 322 KB
8T49N24x Frequency Programming Guide Application Note PDF 198 KB
AN-893 8T49N241_2 Frequency Synchronization Compliance Report Application Note PDF 1.11 MB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN#: TP1901-01 Datasheet Correction for I2C Read Sequence Diagrams for the UFT Product Family Product Change Notice PDF 454 KB
PCN# : N1807-01 Die revisionc change, 8T49N240, 8T49N242 Product Change Notice PDF 21 KB
IDT Products for Wired Broadband Applications Application Briefs PDF 686 KB
8T49N24x Example Timing Commander Configuration and Phase Noise Plots Miscellaneous ZIP 1.04 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Jitter Attenuator Product Overview 简体中文 Overview PDF 1.95 MB
8T49N24x Design Files (Schematic Symbol and PCB Footprint) PCB Design Files ZIP 12 KB
8T49N240 Sub-200fs Universal Frequency Translator Product Brief PDF 322 KB
82P33714/31 SETS and 8T49N24x Universal Frequency Translators Product Brief Product Brief PDF 370 KB
8T49N24x Schematics Review Checklist Schematic XLSX 550 KB
8T49N24x EVB Schematic Schematic PDF 74 KB
IDT Clocks for Xilinx Ultrascale FPGAs Technical Brief PDF 256 KB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB
IDT Clocks for SMPTE and Xilinx® 7 Series FPGAs Technical Brief PDF 566 KB


Title language Type Format File Size Date
Timing Commander Installer (v1.16.4) Software ZIP 19.79 MB
8T49N24x Timing Commander Personality File (v1.7.2) Software Tool ZIP 6.91 MB
8T49N240 IBIS Model Model - IBIS ZIP 331 KB
8T49N24x Design Files (Schematic Symbol and PCB Footprint) PCB Design Files ZIP 12 KB

Boards & Kits

Part Number Title Type Company
8T49N240-EVK Evaluation Kit for 8T49N240 Evaluation Renesas