The 8T49N240 has one fractional-feedback PLL that can be used as a frequency translator with jitter attenuation or a frequency synthesizer. It is equipped with three integer and one fractional output dividers, allowing the generation of up to two different output frequencies, ranging from 8kHz to 1GHz. Output frequencies can be completely independent of the input frequencies, two of these frequencies can be completely independent of each other and the other two will be integer-related to one of the other two frequencies. The four outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels.
The 8T49N240 is ideal for use in a wide range of equipment, including 10G/40G/100G SONET/SDH and Ethernet network line cards, wireless base station baseband units, broadcast video, carrier Ethernet switches, OTN, or in test and measurement applications. For example, the 8T49N240 can be used in GbE/10GbE/100GbE Synchronous Ethernet line card applications in order to preserve the G.8262 compliance from the Synchronous Equipment Timing Source (SETS) on the timing card. The 8T49N240 provides a 200fs (typical, 12kHz to 20MHz) RMS jitter performance that provides users with additional margin in their designs.
Renesas’ third generation Universal Frequency Translator family also includes the 8T49N241 (2-in / 1-PLL / 4-out), 8T49N242 (2-in / 1-PLL / 4-out), the 8T49N285 (2-in / 1-PLL / 8-out), the 8T49N286 (4-in / 2-PLL / 8-out) and the 8T49N287 (2-in / 2-PLL / 8-out). These devices are complemented by the 82P33714 and 82P33731 synchronous equipment timing source (SETS) for Synchronous Ethernet (SyncE) and 10G-40G SyncE, respectively.
To see other devices in this product family, visit the Universal Frequency Translators page.
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Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
An overview of the IDT® 8T49N240, highly-programmable clock generator and jitter attenuator IC. The device features less than 200fs of phase noise, providing valuable system design margin for 10Gbps interfaces in wireline and wireless communication networks. The additional phase noise margin eases system design constraints, allowing engineers to minimize bit error rates (BER) while lowering overall system costs.
The 8T49N240 is the latest member of IDT's third-generation Universal Frequency Translator (UFT™) family. It features the ability to produce virtually any common output frequency from virtually any input frequency. The highly-flexible, high-performance clock generator and jitter attenuator is ideal for 10Gbps or multi-lane 40Gpbs / 100Gbps timing applications where 300fs of phase noise is typically the maximum acceptable amount allowed at the physical ports. The 200fs phase noise specification of the 8T49N240 provides ample noise margin, enabling engineers to simplify their clock tree designs and utilize lower cost PCBs.
The 8T49N240 is complemented by IDT's proven Timing Commander™ software – a free, intuitive program that allows users to configure the device with ease by simply clicking on blocks, entering desired values, and sending the configuration to the device. IDT also offers a web-based tool that allows customers to generate custom part numbers in seconds to match their specific configurations.
The 8T49N240 features a 6 x 6 mm package footprint, requiring considerably less PCB area than most other solutions with this level of performance and flexibility. The device is also suitable for 25/28Gbps interfaces.
The 8T49N240 and evaluations boards are available now. Visit https://www.IDT.com/8T49N240 to learn more and request samples. For more information learn more about IDT's industry-leading portfolio of programmable clock generators, or contact your local IDT sales representative.
|Benefits of a Point-of-Use Clock for Jitter Optimization||Blog Post||Apr 27, 2021|
|Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility||Blog Post||Jun 14, 2019|
|IDT's Flexible Timing Solution Provides Valuable Design Margin for 10Gbps, and 40/100Gbps Multi-lane Interfaces||News||Jul 3, 2017|