Renesas jitter attenuators make use of a low-jitter external reference and control circuitry to remove unwanted noise from one or more input clock signals. Different members of this category of products make use of VCXOs or simple crystals as this reference. Innovative techniques allow the use of fixed-frequency crystals rather than hard-to-find pullable crystal devices. In addition, the jitter attenuator products also include a frequency translation stage that allows the output frequency or frequencies to be different than the input frequency. This input-output frequency may be an integer or non-integer ratio depending on the device selected. Several devices within the family will allow multiple such ratios to be supported, resulting in multiple independent frequencies or even non-integer relationships between output frequencies.

The integration of a jitter attenuator and frequency translator simplifies the circuit and minimizes the bill-of-materials (BOM). Renesas' rich portfolio of jitter attenuators and frequency translators come in varying levels of performance, power, and programmability to address the needs of virtually any application. Renesas jitter attenuators support various single-ended and differential signaling levels such as LVCMOS, LVPECL, LVDS, HCSL, HSTL, or SSTL.

Customers looking for application-specific signal repeaters and retimers for PCIe, SAS/SATA, USB 3.0, and XAUI applications, please visit our Signal Integrity Products page.

Applications and Standards


What is a Jitter Cleaner?

A jitter cleaner (a.k.a. jitter attenuator) is a device that is used to reduce the magnitude of noise (jitter) on a given timing signal. Jitter can be described as the undesired deviation from an ideal periodic timing signal. Jitter is commonly observed in characteristics such as the phase, or amplitude of successive pulses, and/or changes in frequency over a given time frame. High levels of jitter often result from long traces, cabling, and noisy system environments. Excessive levels of Jitter cause undesired system behavior in high-performance applications. Renesas jitter cleaners (jitter attenuators) rely on stable reference sources and innovative control circuitry to lock on to the phase and average frequency of a noisy clock signal and then output a high-quality (low jitter) signal to be sourced to ‘downstream’ devices within the clock network.


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ClockMatrix™2 System Synchronizer Overview

The ClockMatrix™ 2 family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 800Gbps interface speeds. This second-generation family delivers improved performance with phase jitter as low as 88fs RMS. The highly integrated devices serve as full-function IEEE 1588 synchronization clocks and ultra-low jitter reference clocks for synchronous Ethernet PHYs with data rates up to 112Gbps PAM-4, reducing design complexity and bill of materials (BOM). Visit to learn more.