Radio Access Network Equipment Synchronizer - Six Channels
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Overview
Description
The RC38612 RAN synchronizer regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on wireless baseband, DU, CU, RU, fronthaul or backhaul networks. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generationi including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC and IEEE 1588 TSUs.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
Features
- Six independent timing channels
- Jitter output below 150fs RMS (typical)
- Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
- DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
- DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
- IEEE 1588 Support:
- Precise (1ps) resolution for phase measurement and control
- All outputs/inputs can be configured to decode/encode PWM clock signals
- PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
- Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I2C EPROM via separate I2C Master Port
Applications
Documentation
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Device Errata
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Guide
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Guide
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Guide
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Other
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Overview
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Overview
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Product Change Notice
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Product Change Notice
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Schematic
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White Paper
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Design & Development
Software & Tools
Boards & Kits
Boards & Kits
Evaluation Kit for RC38612 and RC32012 ClockMatrix
This is the evaluation kit for the Renesas RC38612 ClockMatrix Radio Access Network Equipment Synchronizer. This is the superset device and can also be used to evaluate...
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Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Processing table
| -40 to 85°C | Reel | ||
| -40 to 85°C | Reel | ||
| -40 to 85°C | Tray |
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play_circle_filledVideos & Training
IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)
Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds.
They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.
For more information, visit www.idt.com/clockmatrix.
Video List
News & Blog Posts
| Selecting the Best Device for Converter Clocking Applications | Blog Post | Feb 1, 2022 |