The 8T39204 is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

特長

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following input levels: LVPECL, LVDS, HCSL, HSTL, and single-ended
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Maximum Output Frequency:
    • LVPECL – 1.5GHz
    • LVDS – 1.5GHz
    • HCSL – 250MHz
    • LVCMOS – 250MHz
  • Two banks, each has two differential output pairs that can be configured as LVPECL, LVDS, or HCSL
  • One single-ended reference output with synchronous enable to avoid clock glitch
  • Output skew: 81ps (maximum), Bank A and Bank B at the same output level
  • Part-to-part skew: 200ps (typical), design target
  • Additive RMS phase jitter at 156.25MHz, (12kHz–20MHz): 37.6fs (typical), 3.3V/3.3V
  • Supply voltage modes:
    • VDD/VDDO
    • 3.3V/3.3V
    • 3.3V/2.5V
    • 2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • 5 × 5 mm 32-VFQFPN lead-free (RoHS 6) packaging

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
star 8T39204 Datasheet データシート PDF 719 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
Clock Distribution Overview 概要 PDF 217 KB
IDT Clock Generation Overview 概要 PDF 1.83 MB

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