概要

The 9DB823 is compatible with the Intel DB800Q Differential Buffer Specification. This buffer provides 8 PCI-Express SRC or 8 QPI clocks. The 9DB823 is driven by a differential output pair from a CK410B+ or CK509B main clock generator.

9DB823 - Block Diagram
9DB823 - Pinout
9DB823 - Block Diagram
9DB823 - Pinout
  • 8 - 0.7 V HCSL differential output pairs
  • Phase jitter: PCIe Gen2 < 3.1 ps rms
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 50-140 MHz operation in PLL mode
  • 33-400 MHz operation in Bypass mode

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9DB823BFLF
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Tube
    9DB823BFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Reel
    9DB823BGLF
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 C Yes Tube
    9DB823BGLFT
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 C Yes Reel
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    ビデオ&トレーニング

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview