The 9ZXL0832E is a second-generation, enhanced performance DB800ZL differential buffer. The part is pin-compatible to the 9ZXL0831A while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. The 9ZXL0832E has an SMBus Write Lockout pin for increased device and system security.
 

Features

  • SMBus write lock feature; increases system security
  • PCIe Gen 1–5 compliance
  • LP-HCSL outputs; eliminate 16 resistors, save 27mm² of area
  • 8 OE# pins; hardware control of each output
  • Selectable PLL BW; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
  • Spread spectrum compatible; tracks spreading input clock for EMI reduction
  • 100MHz and 133.33MHz PLL Mode; UPI and legacy QPI support
  • 6 × 6 mm 48-VFQFPN package; small board footprint
 

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL0832EKILF
Package Info
 Active VFQFPN 48 I Yes Tray
Availability

Buy / Quote
9ZXL0832EKILFT
Package Info
 Active VFQFPN 48 I Yes Reel
Availability
Buy / Quote

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZXL06x2E-9ZXL08xxE-9ZXL12x2E Family Datasheet – Datasheet PDF 495 KB
Application Notes & White Papers
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 – Application Note PDF 244 KB
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-828 Termination - LVPECL – Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers – Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination – Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
Downloads
9ZXL0832E IBIS Model – Model - IBIS ZIP 20 KB
Other
PCI Express Timing Solutions Overview – Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

Boards & Kits

Part Number Title Type Company
EVK9ZXL1951D Evaluation Kit for 19-Output DB1900Z for PCIe Gen1-4 and QPI/UPI Evaluation Renesas

News & Additional Resources

Type Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 18, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 28, 2017
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped News Dec 18, 2014