概要

The IDT5V41285 is a PCIe Gen2 compliant clock generator. The device has 2 differential HCSL outputs. The output frequency is selectable via select pins.

5V41285 Block Diagram
5V41285 Pinout Diagrams
5V41285 Block Diagram
5V41285 Pinout Diagrams
  • 16-pin TSSOP and VFQFPN packages; small board footprint
  • Outputs can be terminated to LVDS; can drive a wider variety of devices
  • OE control pin; greater system power management
  • Industrial temperature range available; supports demanding embedded applications
  • Cycle-to-cycle jitter: 80ps
  • Output-to-output skew <50 ps
  • PCIe Gen2 phase jitter <3.0ps RMS
  • Low phase noise: 12kHz to 20MHz <6ps
  • For PCIe Gen3 applications, see the IDT5V41315

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    5V41285NLGI
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 16 I Yes Tray
    5V41285NLGI8
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 16 I Yes Reel
    5V41285PGGI
    circle廃止品
    memory
    view_in_ar
    		TSSOP 16 I Yes Tube
    5V41285PGGI8
    circle廃止品
    memory
    view_in_ar
    		TSSOP 16 I Yes Reel
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    ビデオ&トレーニング

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview