概要

The IDT6V31021 is a 4-output low- power differential buffer. Each output has its own OE# pin. It has a maximum operating frequency of 167 MHz and supports all SERDES clock frequencies for Freescale QorIQ CPUs.

6V31021 - Block Diagram
6V31021 - Pinout
6V31021 - Block Diagram
6V31021 - Pinout
  • 4 - low power differential output pairs
  • Individual OE# control of each output pair
  • Low power differential outputs
  • Power down mode when all OE# are high
  • Industrial temperature range
  • 20-pin MLF
  • Output cycle-cycle jitter <15 ps additive
  • Output to Output skew: <50 ps
  • PCIe Gen3 additive phase jitter <0.3 ps rms
  • 10.3125G / 64 additive phase jitter <100 fs rms

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    6V31021NLGI
    circle新規採用非推奨品
    memory
    view_in_ar
    		VFQFPN 20 I Yes Tray 1 3.253
    6V31021NLGI8
    circle新規採用非推奨品
    memory
    view_in_ar
    		VFQFPN 20 I Yes Reel 1
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    ビデオ&トレーニング

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview