概要

The 557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs.

557-06 - Block Diagram
557-06 - Pinout
557-06 - Block Diagram
557-06 - Pinout
  • Packaged in 20-pin TSSOP
  • Pb (lead) free packaging
  • Operating voltage of 3.3 V
  • Low power consumption
  • Input differential clock of up to 200 MHz
  • Jitter 60 ps (cycle-to-cycle)
  • Output-to-output skew of 50 ps
  • Available in industrial temperature range (-40 to +85°C)
  • For PCIe Gen2/3 applications, see the 5V41067A

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Moisture Sensitivity Level (MSL)
    Price (USD) | 1ku
    ご購入 / サンプル
    型名
    557G-06LF
    circle新規採用非推奨品
    memory
    view_in_ar
    今すぐ購入する
    		TSSOP 20 C Yes Tube 1 3.806
    557G-06LFT
    circle新規採用非推奨品
    memory
    view_in_ar
    		TSSOP 20 C Yes Reel 1
    557GI-06LF
    circle新規採用非推奨品
    memory
    view_in_ar
    今すぐ購入する
    		TSSOP 20 I Yes Tube 1 3.976
    557GI-06LFT
    circle新規採用非推奨品
    memory
    view_in_ar
    		TSSOP 20 I Yes Reel 1
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    ビデオ&トレーニング

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview