8V19N882 Evaluation Kit
The evaluation kit supports the electrical evaluation process of the 8V19N882NVGI JESD204B/C clock jitter attenuator for all major device parameters including phase...
The 8V19N882 is a fully integrated FemtoClock® RF Sampling Clock Generator and Jitter Attenuator designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in 4G, 5G and including mmWave radio implementations.
The device supports JESD204B (subclass 0 and 1) and JESD204C. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for the best possible phase noise characteristics. The second stage PLL locks on the first PLL output signal and synthesizes the target frequency. The second stage PLL can use the internal or an external high-frequency VCO.
The device generates the high-frequency clocks and the low-frequency synchronization signals (SYSREF) from the selected VCO. SYSREF signals are internally synchronized to the clock signals. The integrated signal delay blocks can be used to achieve phase alignment, controlled phase offsets between system reference and clock signals and to align/delay individual output signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility.
The device is configured through a 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via the GPIO[1:0] outputs. Internal status bit changes can also be reported via a GPIO output.
For information regarding evaluation boards and material, please contact your local sales representative.
|Datasheet||PDF 1.08 MB|
|Application Note||PDF 91 KB|
|Guide||PDF 413 KB|
|Application Note||PDF 1.99 MB|
|Overview||PDF 331 KB|
|Application Note||PDF 495 KB|
|Application Note||PDF 115 KB|
|Application Note||PDF 233 KB|
|Application Note||PDF 565 KB|
|Application Note||PDF 438 KB|
|Software & Tools - Other||TCP 5.19 MB|
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
|Demystifying 5G – Phase noise of clock and LO components in 5G base stations||External Link|
|Demystifying 5G – Timing alignment and delay adjustment of SYSREF and sampling clock signals in 5G base stations||External Link|
|Demystifying 5G – Clock input monitoring, holdover and relocking in 5G base stations||External Link|
The 8V19N880 and 8V19N882 JESD204B/C clock jitter attenuators deliver low phase noise and exceptional jitter performance as low as 74fs RMS and -90dB spurious attenuation for mission-critical industrial data converter applications in wireless radio, test and measurement, instrumentation, and high-performance imaging. They support frequencies up to 3932.16MHz (up to 6GHz with an external VCO) and feature 16 and 18 integrated differential outputs to deliver a first-in-class balance of high performance, low voltage and low power consumption with 1.8V support.