Overview

Description

The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Twelve low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential
    input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control input select pins
  • Output skew: 40ps (max)
  • Propagation delay: 310ps (typical)
  • Low additive phase jitter, RMS; fREF = 156.25MHz,
    10kHz - 20MHz: 77fs (typical)
  • Maximum device current consumption (IDD): 213mA
  • 2.5V supply voltage
  • Lead-free (RoHS 6), 40-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

Applications

Documentation

Title Type Date
PDF1.77 MB
Datasheet
PDF1.99 MB
Application Note
PDF170 KB
Application Note
PDF133 KB
Application Note
PDF495 KB
Application Note
PDF442 KB
Application Note
PDF180 KB
Application Note
PDF153 KB
Application Note
PDF120 KB
Application Note
PDF565 KB
Application Note
PDF121 KB
Application Note
PDF331 KB
Overview
PDF217 KB
Overview
PDF1.83 MB
Overview
PDF739 KB
Product Brief
PDF378 KB
Product Brief
PDF728 KB
Product Change Notice
PDF983 KB
Product Change Notice
PDF36 KB
Product Change Notice
PDF31 KB
Product Change Notice

Design & Development

Models