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SH7750R

The SH7750R is a 32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with SH-1, SH-2, and SH-3 microcomputers. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation look aside buffer). The SH7750R has a 16-kbyte instruction cache and a 32-kbyte data cache.

The SH7750R has an on-chip bus state controller (BSC) that allows connection to DRAM and synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be reduced by almost 50% compared with 32-bit instructions.

 

Key Features:

  • Operating frequency
    • 200/240MHz
  • Cache
    • Large capacity Cache:16kB instruction + 32kB data
    • (2way set associative)
  • Debug
    • H-UDI, UBC
  • Package
    • BGA-256
    • QFP-208
  • Other features
    • 64-bit bus interface
    • Pin compatible with the SH7750/SH7750S
    • Designated 2-way cache, 1.5-2 times more efficient than conventional products due to 2X increase in capacity
    • Due to the use of FPU in DSP processing, MP3s (etc.) can be processed

     

Pin Count / Memory Size Lineup:

Below you will find information to support the development of your application.
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Hardware Design Support

Title Description
IBIS/BSDL

IBIS standard simulation data is required for high-speed board design and can be used to run simulations to examine and troubleshoot issues such as waveform reflection, ringing, and so on, before producing the actual board.

BSDL is a data input format supported by most IEEE 1149.1 (JTAG)-compliant tools. The automatic test pattern generation (ATPG) and automatic test equipment functions of these tools facilitate testing.

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