The 8A34011 Line Card Synchronizer for IEEE 1588 regenerates and distributes ultra-low jitter; precision timing signals that are locked to IEEE 1588 and Synchronous Ethernet (SyncE) reference sources elsewhere in a system. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media that introduce clock propagation delays. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 TSUs in a system. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.


  • Eight independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 1kHz to 1GHz
  • DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Supports up to 8 differential or 16 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port


製品名 Part Status Temp. Range Carrier Type 購入/サンプル
Active -40 to 85°C Reel
Active -40 to 85°C Tray


タイトル 他の言語 分類 形式 サイズ 日付
8A3xxxx Firmware Version v4.8.7 Errata Notice エラッタ PDF 38 KB
8A34011 Datasheet データシート PDF 1.94 MB
8A3xxxx Family Errata (Rev B with Update v4.7) エラッタ PDF 127 KB
8A3xxxx Firmware Version v4.8.7 Release Notes ガイド PDF 143 KB
8A3xxxx Family Programming Guide (v4.8.7) ガイド PDF 2.33 MB
8A3xxxx Family Programming Guide (v4.8) ガイド PDF 3.60 MB
8A34xxx 144BGA EVK User Manual マニュアル-評価ボード PDF 2.67 MB
ClockMatrix GUI Step-by-Step User Guide ガイド PDF 4.98 MB
Using a Frame or Sync Pulse Input for Clock Alignment アプリケーションノート PDF 1.57 MB
Aligning 1PPS Clocks in Larger Chassis Systems アプリケーションノート PDF 1.62 MB
ClockMatrix: Methods for Changing DPLL Settings during a Reference Switch アプリケーションノート PDF 354 KB
AN-807 Recommended Crystal Oscillators for Network Synchronization アプリケーションノート PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter アプリケーションノート PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 アプリケーションノート PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix アプリケーションノート PDF 880 KB
Auto-Alignment of Outputs アプリケーションノート PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback アプリケーションノート PDF 155 KB
ClockMatrix Firmware Update through Serial Port and EEPROM v1.0 アプリケーションノート PDF 739 KB
AN-1033 Delay Variation Measurement and Compensation アプリケーションノート PDF 633 KB
AN-1031 Time Alignment Background in Wireless Infrastructure アプリケーションノート PDF 479 KB
AN-1032 Time-of-Day Within an Ideal Chassis-Based System アプリケーションノート PDF 442 KB
AN-1034 Minimizing Backplane Signal Usage アプリケーションノート PDF 566 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment アプリケーションノート PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy アプリケーションノート PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment アプリケーションノート PDF 324 KB
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 製品変更通知 PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue 製品変更通知 PDF 123 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products 製品変更通知 PDF 435 KB
Timing Commander Installer (v1.16.4) ソフトウェア ZIP 19.79 MB
ClockMatrix Register Header Files v4.8.7 ソフトウェア ZIP 278 KB
ClockMatrix Firmware (v4.8.7) Trigger Registers, v1.1 ソフトウェア ZIP 73 KB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.2, FWv4.8.7) ソフトウェア ZIP 47.13 MB
8A340xx ClockMatrix IBIS Model モデル-IBIS ZIP 2.40 MB
8A34011 BSDL Model モデル-BSDL ZIP 3 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 ソフトウェア ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 ソフトウェア ZIP 177 KB
8A340x1 BSDL Model モデル-BSDL BSDL 15 KB
ClockMatrix BGA-144 Delphi Thermal Model with 1W Power モデル-サーマル PDML 3 KB
ClockMatrix BGA-144 2-Resistor Thermal Model with 1W Power モデル-サーマル PDML 2 KB
8A3x0xx Schematic Checklist (v1.23) その他 XLSX 318 KB
ClockMatrix Family Overview 概要 PDF 285 KB
ClockMatrix 144-BGA Devices Evaluation Board Schematic v1.1 回路図 PDF 288 KB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB