The 9ZXL0451 is a second generation enhanced performance DB800ZL derivative for PCIe Gen4 and 5 applications. In fanout (bypass) mode, it is DB2000Q compatible. A fixed external feedback in ZDB mode maintains low drift for critical QPI/UPI.
 

Features

  • LP-HCSL outputs eliminate 16 resistors; save 32mm2 of area
  • PCIe Gen 1–5 compliance
  • 4 OE# pins; SMBus control also available
  • 3 selectable SMBus addresses
  • 2 selectable ZDB bandwidths; minimizes jitter peaking in cascaded PLL topologies
  • Hardware/SMBus control of ZDB bandwidth and fanout modes
  • Spread spectrum compatible
  • 100MHz ZDB mode
  • 5 × 5 mm 32-VFQFPN package; small board footprint

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL0451EKILF
Package Info
 Active VFQFPN 32 I Yes Tray
Availability

Buy / Quote
9ZXL0451EKILFT
Package Info
 Active VFQFPN 32 I Yes Reel
Availability
Buy / Quote

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZXL04x1E-9ZXL06x1E-9ZXL08x1E-9ZXL12x1E Family Datasheet – Datasheet PDF 475 KB
Application Notes & White Papers
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 – Application Note PDF 244 KB
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-828 Termination - LVPECL – Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers – Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination – Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
Downloads
9ZXL0451E IBIS Model – Model - IBIS ZIP 16 KB
Other
PCI Express Timing Solutions Overview – Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Type Date
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 21, 2018
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 18, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 28, 2017
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped News Dec 18, 2014