概要
説明
The 82V3203A is an integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) for Stratum 3, SMC, 4E and 4 clocks in SONET/SDH equipment, DWDM, and wireless base stations, such as GSM, 3G, DSL concentrator, router, and access network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing, and external synchronization reference timing. An input clock is automatically or manually selected for DPLL locking. The DPLL supports three primary operating modes: Free-Run, Locked, and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths, 0.1Hz to 560Hz in 11 steps, and damping factors, 1.2 to 20 in 5 steps. Different settings cover all SONET/SDH clock synchronization requirements. A highly stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ± 741ppm. All the read/write registers are accessed only through an I2C programming interface.
特長
- Features 0.1Hz to 560Hz bandwidth
- Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/Option I) jitter generation requirements
- Provides node clocks for cellular and WLL base stations (GSM and 3G networks)
- Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing-based ADSL equipment
- Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
- Employs DPLL and APLL to feature excellent jitter performance and minimize the number of external components
- Supports Forced or Automatic operating mode switch controlled by an internal state machine
- The primary operating modes are Free-Run, Locked, and Holdover
- Supports programmable DPLL bandwidth (0.1Hz to 560Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps)
- Supports 1.1X10-5ppm absolute holdover accuracy and 4.4X10-8ppm instantaneous holdover accuracy
- Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61ns
- Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
- Limits the phase and frequency offset of the outputs
- Supports manual and automatic selected input clock switch
- Supports automatic hitless selected input clock switch on clock failure
- Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing, and external synchronization reference timing
- Provides three 2kHz, 4kHz, or 8kHz frame sync input signals, and 2kHz and 8kHz frame sync output signals
- Provides three input clocks whose frequency cover from 2kHz to 155.52MHz
- Provides two output clocks whose frequency cover from 1Hz to 622.08MHz
- Provides output clocks for BITS, GPS, 3G, GSM, etc.
- Supports CMOS input/output and PECL/LVDS output technologies
- Supports master clock calibration
- Supports line card application
- Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813, and ITU-T G.783 criteria
- I2C programming interface
- IEEE 1149.1 JTAG Boundary Scan
- Single 3.3V operation with 5V tolerant CMOS I/Os
- 68-pin VFQFPN package, Green package options available
製品比較
アプリケーション
ドキュメント
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| 分類 | タイトル | 日時 |
| 製品変更通知 | PDF 43 KB | |
| 製品変更通知 | PDF 140 KB | |
| 製品変更通知 | PDF 398 KB | |
| EOL通知 | PDF 302 KB | |
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設計・開発
モデル
ECADモデル
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| VFQFPN | 68 | C | No | Tray | ||
| VFQFPN | 68 | C | Yes | Tray |
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