Overview

Description

The 72V51253 multi-queue flow-control device is a single chip within which between 1 and 4 discrete FIFO queues can be setup. All queues within the device have common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user.

Features

  • Total Available Memory = 2,359,296 bits
  • Available Memory in blocks of 512 x 18 or 1,024 x 9
  • Independent Read and Write access per queue
  • 100% Bus Utilization, Read and Write on every clock cycle
  • 166 MHz High speed operation (6ns cycle time)
  • 3.7ns access time
  • Individual, Active queue flags (OV, FF, PAE, PAF)
  • Global Bus Matching - (All Queues have same Input Bus Width
  • and Output Bus Width)
  • User Selectable Bus Matching Options:
  • - x18in to x18out - x9in to x18out - x18in to x9out - x9in to x9out
  • FWFT mode of operation on read port
  • JTAG Functionality (Boundary Scan)
  • Available in a 256-pin PBGA package
  • Industrial temperature range (-40C to +85C) is available

Documentation

Document title Document type
Type
Date Date
PDF 554 KB Datasheet
PDF 142 KB Application Note
PDF 167 KB Application Note
PDF 112 KB Application Note
PDF 217 KB Application Note
TXT 11 KB Application Note
PDF 123 KB Guide
PDF 24 KB Product Change Notice
PDF 80 KB Product Change Notice
PDF 38 KB Product Change Notice
PDF 211 KB Product Change Notice
PDF 26 KB Product Change Notice
12 items

Design & Development

Models

Models

Title Type Type Date Date
ZIP 2 KB Model - BSDL
1 item

Support