The 8A34041 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
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Type | Title | Date |
Datasheet | PDF 2.15 MB | |
Application Note | PDF 247 KB | |
Application Note | PDF 465 KB | |
Product Change Notice | PDF 502 KB | |
Application Note | PDF 164 KB | |
Manual - Software | PDF 215 KB | |
Guide | PDF 2.54 MB | |
Application Note | PDF 1.57 MB | |
Application Note | PDF 57 KB | |
Application Note | PDF 275 KB | |
Other | XLSX 321 KB | |
Guide | PDF 936 KB | |
Application Note | PDF 1.16 MB | |
Application Note | PDF 70 KB | |
Overview | PDF 320 KB | |
Application Note | PDF 1.92 MB | |
Release Note | PDF 103 KB | |
Product Change Notice | PDF 135 KB | |
Application Note | PDF 692 KB | |
Application Note | PDF 2.13 MB | |
Guide | PDF 10.53 MB | |
Product Change Notice | PDF 113 KB | |
Guide | PDF 2.35 MB | |
Guide | PDF 213 KB | |
Application Note | PDF 393 KB | |
Application Note | PDF 556 KB | |
Application Note | PDF 231 KB | |
Application Note | PDF 552 KB | |
Application Note | PDF 385 KB | |
Application Note | PDF 272 KB | |
Application Note | PDF 406 KB | |
Application Note | PDF 304 KB | |
Device Errata | PDF 38 KB | |
Guide | PDF 143 KB | |
Application Note | PDF 354 KB | |
Guide | PDF 2.35 MB | |
Application Note | PDF 390 KB | |
Manual - Hardware | PDF 486 KB | |
Application Note | PDF 880 KB | |
Application Note | PDF 584 KB | |
Product Change Notice | PDF 301 KB | |
Application Note | PDF 162 KB | |
Application Note | PDF 550 KB | |
Application Note | PDF 739 KB | |
Application Note | PDF 633 KB | |
Product Change Notice | PDF 123 KB | |
Product Change Notice | PDF 435 KB | |
Application Note | PDF 479 KB | |
Application Note | PDF 442 KB | |
Application Note | PDF 566 KB | |
Manual - Hardware | PDF 2.67 MB | |
Application Note | PDF 976 KB | |
Application Note | PDF 659 KB | |
Schematic | PDF 288 KB | |
54 items
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Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Select an orderable part number:
Orderable Part ID | Sample |
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8A34041E-000AJG | Availability |
The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds. They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.
The 8A3404x Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) family provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI). The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources.
The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces
For more information, visit www.idt.com/clockmatrix.