Programmable PhiClock™ Generator
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Overview
Description
The 9FGV1004 is a member of Renesas' PhiClock™ programmable clock generator family. The 9FGV1004 provides 1 copy each of 2 integer-related frequencies, 2 copies of a fractional or spread-spectrum frequency and 2 copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.
Features
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PCIe Gen1–4 compliant
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267fs RMS typical phase jitter at 156.25MHz (12kHz–20MHz)
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4 programmable output pairs plus 2 LVCMOS REF outputs
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2 integer and 1 fractional or spread-spectrum output per configuration
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1MHz–325MHz integer outputs (LVDS or LP-HCSL)
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1MHz–200MHz integer outputs (LVCMOS
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1.8V to 3.3V core VDD
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Individual 1.8V to 3.3V VDDO for each programmable output pair
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Supports HCSL, LVDS and LVCMOS I/O standards
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Supports AC-coupled LVPECL and CML logic – see AN-891
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4 × 4 mm 24-VFQFPN and 24-LGA packages with 50MHz integrated crystal option
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Supported by Timing Commander™ software
Applications
Documentation
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Datasheet
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Application Note
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Datasheet
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Datasheet
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Manual - Software
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Manual - Software
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Other
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Overview
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Overview
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PDF734 KB
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Product Change Notice
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Product Change Notice
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Product Change Notice
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Product Change Notice
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Schematic
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Design & Development
Software & Tools
Boards & Kits
Boards & Kits
Evaluation Kit for 9FGV1004 Programmable PhiClock™ Generator
This is the evaluation board for the 9FGV1004 programmable PhiClock™ generator. It provides a convenient way of configuring and programming the blank parts for the...
Featured Documents:
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
This device is factory-configurable. Try the Custom Part Configuration Utility.
Processing table
Part Number |
Output Type |
Output Freq Range (MHz) |
Supply Voltage (V) |
Xtal Freq (MHz) |
Pkg. Type |
Carrier Type |
Buy / Sample |
|---|---|---|---|---|---|---|---|
| LP-HCSL, LVDS | 50, 100, 125, 156.25 | 1.8, 3.3 | 50 | VFQFPN | Tray | Get Samples, | |
| LP-HCSL, LVDS | 50, 100, 125, 156.25 | 1.8, 3.3 | 50 | VFQFPN | Reel | ||
| LP-HCSL, LVDS | 50, 100, 125, 156.25 | 1.8, 3.3 | 50 | LGA | Tray | ||
| LP-HCSL, LVDS | 50, 100, 125, 156.25 | 1.8, 3.3 | 50 | LGA | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
- Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
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- Cart icon to the right of the chip icon: Indicates that samples are available for this product
play_circle_filledVideos & Training
PCIe Reference Clock Jitter Budgets
IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Video List
News & Blog Posts
| Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility | Blog Post | Jun 14, 2019 | |
| IDT Announces World’s Lowest-power PCI Express Timing Family | News | Aug 16, 2012 |
