NOTICE - The following device(s) are recommended alternatives:

The 843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock® VCO. PLL multiplication ratios are selected from internal lookup tables using device input selection pins. The device performance and the PLL multiplication ratios are optimized to support non-FEC (non-Forward Error Correction) SONET/SDH applications with rates up to OC-48 (SONET) or STM-16 (SDH). The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given line card application.

The 843002I-41 includes two clock input ports. Each one can accept either a single-ended or differential input. Each input port also includes an activity detector circuit, which reports input clock activity through the LOR0 and LOR1 logic output pins. The two input ports feed an input selection mux. "Hitless switching" is accomplished through proper filter tuning. Jitter transfer and wander characteristics are influenced by loop filter tuning, and phase transient performance is influenced by both loop filter tuning and alignment error between the two reference clocks.

Typical 843002I-41 configuration in SONET/SDH Systems:

  • VCXO 19.44MHz crystal
  • Input Reference clock frequency selections:
    19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz
  • Output clock frequency selections:
    19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz, 622.08MHz, Hi-Z


  • Two Differential LVPECL outputs
  • Selectable CLKx, nCLKx differential input pairs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels
  • Maximum output frequency: 700MHz
  • FemtoClock VCO frequency range: 560MHz - 700MHz
  • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical)
  • Full 3.3V or mixed 3.3V core/2.5V output operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

tuneProduct Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 32 I Yes Tray
Obsolete VFQFPN 32 I Yes Reel


Title language Type Format File Size Date
Datasheets & Errata
star 843002I-41 Datasheet Datasheet PDF 442 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-841 Pullable Crystal Selection and VCXO Tuning Application Note PDF 334 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-848 VCXO - Crystal Selection Application Note PDF 222 KB
AN-849 Loop Filter Component Selection for VCXO Based PLLs Application Note PDF 218 KB
AN-847 VCXO - Absolute Pull Range Application Note PDF 155 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN Product Discontinuation Notice PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN Product Discontinuation Notice PDF 537 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB


Title language Type Format File Size Date
843002I-41 IBIS Model Model - IBIS ZIP 64 KB

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