
Zero-delay buffers (ZDB) provide a synchronous copy (no propagation delay) of the input clock at the outputs, usually without frequency translation. The Renesas ZDBs are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads offering various signal levels, including LVPECL, LVDS, HCSL, CML, HSTL, SSTL, or LVCMOS. ZDBs are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic, and synchronous memory.
Most zero-delay buffers allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Simple frequency translation is possible with a ZDB when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.
Hint: If more than one unique output frequency is required (eg. 100MHz and 125MHz), make use of the “Output Banks” parametric selector. Each bank corresponds to a unique output frequency.
The Renesas zero-delay buffer (ZDB) IC families are available with a wide range of options and features. Differential outputs such as LVPECL, LVDS, HCSL, CML, HSTL, SSTL, as well as selectable outputs, are supported for output frequencies up to 3.2GHz and single-ended LVCMOS outputs for frequencies up to 350MHz. In addition, Renesas' PLL portfolio has devices supporting supply voltages from 1.2V up to 3.3V and that are available in the commercial and industrial temperature ranges.
Using a Renesas PLL product has many benefits. Reducing the number of quartz crystals on a board improves reliability because crystals are highly susceptible to shock and vibration. Using a clock signal generator also reduces a customer's board cost and space, bill of materials (BOM) and inventory levels by replacing multiple crystals and oscillators with one device. They are ideal for use in a large variety of systems, from personal computers to consumer electronics or industrial systems, as well as high-performance networking and communications systems.
There are many important factors when choosing a ZDB for a particular application. The following parameters will give users a basic starting point to narrow down the potential solutions:
Description
Brief overview of IDT's zero-delay buffers. Zero-delay buffers (ZDB) are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.
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