The new enhanced Common Public Radio Interface (eCPRI) Mass Multiple-input Multiple-output (MIMO) Remote Radio Unit (RRU) needs low phase noise and spurious performance to avoid channel blocking and interference. The system requires deterministic latency and low phase drift in a clock signal and needs to ensure receiver phase synchronization at a picosecond level. It is the base for accurate beamforming and MIMO architectures. Our solution consists of a system synchronizer, microwave synthesizer, high-performance fanout buffer, and ultra-low noise LDO. It is an optimized design to achieve high timing precision, integration and flexibility that enables developers of 5G compliant networks and systems.

System Benefits​:

  • Highly integrated timing source eliminates the need for additional clock devices
  • Support for synchronized Ethernet (Sync-E), JESD204B/C, and IEEE 1588 G.8262.1 and G.8262 telecom boundary clock requirements and G.8273.2 Class C/D time accuracy
  • High-performance mmWave wideband synthesizer that generates output frequencies up to 18GHz




  • Wireless infrastructure for 5G Mass MIMO network equipment

Winning Combinations Interactive Diagram

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4:3 ratio Sheet.1 Sheet.2 Sheet.3 Sheet.4 CN340 CN340 CN340 Baseband Unit (BBU) Baseband Unit (BBU) Baseband Unit (BBU) DFE Digital Front End DFE Digital Front End DFE Digital Front End Radio Radio Radio CPRI, eCPRI CPRI, eCPRI CPRI, eCPRI Network Network Network Sheet.284 Sheet.285 Sheet.286 Sheet.289 Transceiver Transceiver Transceiver Sheet.273 Sheet.275 Sheet.277 Sheet.278 Sheet.279 Sheet.280 Sheet.281 Sheet.282 Sheet.283 Sheet.288 Sheet.295 Sheet.296 Sheet.298 Sheet.299 Sheet.301 Sheet.307 Sheet.308 Sheet.309 Sheet.310 Connector 1.162 Sheet.312 Connector 1.313 Sheet.314 Sheet.318 Sheet.319 Sheet.320 Sheet.321 Sheet.322 Sheet.323 Sheet.324 Connector 1.162.325 Sheet.326 Sheet.328 Sheet.329 Sheet.330 Sheet.331 Sheet.332 Sheet.333 Sheet.334 Sheet.335 Connector 1.162.336 Sheet.337 Connector 1.338 122.88MHz <80fs RMS 122.88MHz <80fs RMS 122.88MHz <80fs RMS SYSREF SYSREF SYSREF 491.52MHz<80fs RMS 491.52MHz <80fs RMS 491.52MHz<80fs RMS 245.76 MHz 245.76 MHz 245.76MHz 1.2V/<300mA 1.2V/<300mA 1.2V/<300mA 3.3V/286mAmax 3.3V/ 286mAmax 3.3V/286mAmax 8 Communication Lines B.795 8 8 8 2 2 2 2 Sheet.356 5V 5V 5V 2 2 2 2 Sheet.360 SYSREF SYSREF SYSREF 1.8V/<700mA 1.8V/<700mA 1.8V/<700mA 3.3V/<1A 3.3V/<1A 3.3V/<1A 3.3V/1.24Amax 3.3V/ 1.24Amax 3.3V/1.24Amax 8 8 8 8 Sheet.367 Sheet.368 Sheet.369 Antenna-Array Antenna Array Antenna Array Antenna Array.427 Sheet.428 Sheet.429 Sheet.430 Sheet.431 Sheet.432 Sheet.433 Sheet.434 Sheet.435 Sheet.436 Sheet.437 Sheet.438 Sheet.439 Sheet.440 Sheet.441 Sheet.442 Sheet.443 Sheet.444 Sheet.445 Fanout 1 Fanout Fanout Fanout 2 Fanout Fanout LDO x8 LDO x8 LDO x8 LDO x2 LDO x2 LDO x2 LDO 1 LDO LDO LDO 2 LDO LDO LDO 3 LDO LDO RF Conditioning/Amplification RF Conditioning/Amplification RF Conditioning/Amplification RF Synthesizer x8 RF Synthesizer x8 RF Synthesizer x8 ADC ADC ADC Down-Converter Down-Converter Down-Converter DAC DAC DAC Up-Converter Up-Converter Up-Converter Sheet.446 System Synchronizer System Synchronizer System Synchronizer Sheet.315 Sheet.316 Sheet.409 Ultra-low Phase Noise Ultra-low Phase Noise Ultra-low Phase Noise DPLLn DPLLn DPLLn DPLL DPLL DPLL DCO DCO DCO DCOn DCOn DCOn
Exiting Interactive Block Diagram