The Renesas Fast CMOS Technology (FCT) logic family has been designed for use in standard TTL-logic applications. Our fast CMOS devices feature the highest speed logic available and the lowest power dissipation in the industry. The fast CMOS family consists of a variety of products including bus interfaces, buffers, multiplexers, transceivers, and other devices. There are two output configurations available, the industry-standard High drive and the low-noise Balanced drive. All devices come in several speed grades.
A basic CMOS latch circuit has two inputs (SET and RESET) and one output. The device may either be active-high or active-low, which defines whether a logic HIGH or logic LOW signal will trigger the CMOS latch. The purpose of the CMOS latch is to monitor the SET input and once triggered, change and hold the state of the output until it has been reset by the RESET input. In other words, the CMOS latch latches ON once a change of state has been detected on the SET pin (even if just for a moment), and will remain in the ON state until a change of state is detected on the RESET pin.
CMOS latches are designed to be transparent latches because they allow the outputs to follow the inputs as they are transitioning from low to high (or high to low depending on the architecture); it is an immediate change. So, when several transparent latches follow each other (using the same input signal), the signals can propagate through all of them at once. The Renesas low-power fast CMOS latches are ideal for the temporary storage of data. They can be used for implementing memory address latches, I/O ports, and bus drivers.
Note that CMOS latches are similar to flip-flops, but the word “latch” is primarily used for storage elements, while clocked devices are referred to as “flip-flops.” In addition, latches are typically triggered by the voltage level, while flip-flops are typically triggered by the voltage change (or edge). That is, when a latch is enabled it becomes transparent, while a flip-flop's output only changes on a single type (positive going or negative going) of clock edge.
An octal buffer is a standard logic device containing eight identical buffers. The high-impedance inputs significantly reduce current loading to input drivers while the octal buffer outputs offer improved drive and switching noise performance. The Renesas octal buffers (line drivers) are built using an advanced dual metal fast CMOS technology and are designed to be employed as memory, and address drivers, clock drivers, or bus-oriented transmitters/receivers for improved board density.
Bus Width (bits)
Core Voltage (V)
105°C Max. Case Temp.
|16-Bit Buffer/Line Driver||Buffer/Driver||CS48||-55 to 125°C||16||5||A, C|
|16-Bit Bi-Directional Transceiver||Transceiver||CS48||-55 to 125°C||16||5||A, C|
|16-Bit Buffer/Line Driver||Buffer/Driver||PVG48||-40 to 85°C||16||5||A, C, E|
|16-Bit Bi-Directional Transceiver||Transceiver||PAG48, PVG48||-40 to 85°C||16||5||A, C, E|
|18-Bit Register||Register||PVG56||-40 to 85°C||18||5||C|
|3.3V 16-Bit Buffer/Line Driver||Buffer/Driver||PAG48, PVG48||-40 to 85°C||16||3.3||A, C|
|3.3V 16-Bit Transceiver||Transceiver||PAG48||-40 to 85°C||16||3.3||C|
|3.3V 16-Bit Register (3-State)||Register||PAG48||-40 to 85°C||16||3.3||3-state||A, C|
|16-Bit Register (3-State)||Register||PVG48||-40 to 85°C||16||5||3-state||A, C, E|
|3.3V TO 5.0V 16-Bit Translating Transceiver||Other||PAG48, PVG48||-40 to 85°C||16||3.3||Standard|
|Octal Buffer/Line Driver||Buffer/Driver||PSG20||-40 to 85°C||8||5||A, C|
|Octal Bi-Directional Transceiver||Transceiver||PSG20||-40 to 85°C||8||5||A, C|
|Octal Transparent Latch||Transparent Latch||PCG20||-40 to 85°C||8||5||A, C|
|Octal Buffer/Line Driver||Buffer/Driver||PSG20||-40 to 85°C||4||5||C|
|Fast CMOS Octal Buffer/Line Driver||Buffer/Driver||PCG20, PSG20||-40 to 85°C||4||5||A, C|
|Octal Bi-Directional Transceiver||Transceiver||PCG20, PSG20||-40 to 85°C||4||5||A, C|
|3.3V Octal Buffer/Line Driver||Buffer/Driver||PCG20, PSG20||-40 to 85°C||8||3.3||A, Standard|
|3.3V Octal Bi-Directional Transceiver||Transceiver||PGG20||-40 to 85°C||8||3.3||A, Standard|
|Octal Transparent Latch||Transparent Latch||PSG20||-40 to 85°C||8||5||A, C|
|Octal D Register||Register||PSG20||-40 to 85°C||8||5||A, C|
|8-Bit Identity Comparator||Comparator||PCG20, PSG20||-40 to 85°C||8||5||A, C|
|Octal Latched Transceiver||Transceiver||PCG24||-40 to 85°C||8||5||A, C|
|Octal Transparent Latch||Latch||PSG20||-40 to 85°C||8||5||A, C|
|Octal Bus Transceiver (Open-Drain)||Transceiver||PSG20||-40 to 85°C||8||5||A, Standard|
|Octal Bus Transceivers (with 3-state outputs)||Octal Bus Transceivers with 3-state outputs||-40 to 85°C|
|Octal D-Type Transparent Latches (3-State Outputs) Octal D-Type Transparent Latches (Inverted 3-State Outputs)||Octal D-type Transparent Latches with 3-state output||-40 to 85°C|
|Octal Buffers/Line Drivers (with 3-state outputs)||Octal Buffers and Line Drivers with 3-state outputs||-40 to 85°C|
|Octal D-Type Flip-Flops (with 3-state outputs) Octal D-Type Flip-Flops (with inverted 3-state outputs)||Octal D-type Flip-Flops with 3-state output||-40 to 85°C|
|Octal D-Type Transparent Latches (with three-state outputs)||Octal D-type Transparent Latches with Non-inverted 3-state output||-20 to 75°C|
|Document title||Document type Type||Date Date|
|PDF 603 KB||Overview|
|PDF 2.19 MB||Overview|
|PDF 109 KB||Guide|