Renesas clock dividers (clock frequency dividers) provide an output clock signal that is a divided frequency of the input. They can also be used as clock buffers and make multiple copies of the output frequency. Clock divider devices, when used in divide-by-1 mode, can also function as a fanout buffer.

The Renesas "8" series of fanout buffers and clock dividers feature fully differential internal architecture, even devices with single-ended I/Os. This improves jitter due to inherent common-mode noise rejection and improves output skew. The differential circuitry is constant-current and therefore injects less noise into system power supplies than single-ended solutions, reducing EMI compliance concerns.

Clocks & Timing

Product Selection Table

    Processing table
    Part Number
    Function
    Outputs (#)
    Output Type
    Output Freq Range (MHz)
    Input Freq (MHz)
    Inputs (#)
    Input Type
    Output Banks (#)
    Core Voltage (V)
    Output Voltage (V)
    Divider Value
    Output Skew (ps)
    Additive Phase Jitter Typ RMS (fs)
    105°C Max. Case Temp.
    8P79818
    Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs    		 Buffer, Divider 8 CML, HCSL, LVDS, LVPECL 0.000001 - 700 0.000001 - 700 2 LVCMOS, LVDS, LVHSTL, LVPECL 2 1.8, 2.5, 3.3 1.5, 1.8, 2.5, 3.3 2, 511 100 60
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    Documentation

    Title Type Date
    Clock Distribution Overview
    PDF217 KB
    Overview
    Single-Ended Fanout Buffers and Dividers by IDT

    Description

    Overview of IDT's single-ended fanout buffers and single-ended fanout dividers. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. The clock fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.

     

    Transcript

    Thank you for joining us for an overview of IDTs Fanout Buffers. My name is Vik Chaudhry, I'm Marketing Manager for IDT's Timing Products.
     
    Now, let's consider some single-ended Buffers. In this example we have a differential signal or a crystal input coming in that is fanned out to ten single-ended LVCMOS signals. Typically, the differential inputs can accept either LDVS, LVPECL, HCSL, or HSTL levels. 
     
    This is an example of a very flexible device where one, we have a mux at the input stage, two, we have two sets of dividers that are independent of each other, and three, there are two sets of fanout buffers for each of the banks, with an able signal for each bank.
     
    IDT has a very large portfolio of fanout and clock distribution devices. To make it easy to select these parts, we have developed the collateral that can be used. This collateral is located on the IDT website under our clock and timing products, and if you look under fanout buffers and dividers, you will see this collateral available.
     
    We also have an excellent application support for all the clocks and clock distribution devices.  Most of our products include IBIS models, we also have application notes for various termination schemes, filter recommendations, and we also review schematics. If you have any questions, please feel free to either drop us an email at TSD-Applications@IDT.com or clocks@IDT.com.
     
    Thank you for choosing IDT timing products.
    Video List
    Single-Ended Fanout Buffers and Dividers by IDT