The 813253 is a PLL based synchronous clock generator that is optimized for Gigabit Ethernet and PCI Express®™ clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high frequency Gigabit Ethernet or PCI Express®™ output clock. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in Gigabit Ethernet and PCI Express® applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics.


  • Three differential LVPECL output pairs
  • One differential input supports the following input types: LVPECL, LVDS, LVHSTL, HCSL
  • Accepts input frequencies from 19.6MHz to 136MHz, including: 25MHz, 62.5MHz, 100MHz and 125MHz input clocks
  • Attenuates the phase jitter of the input clock by using a low-cost fundamental mode VCXO crystal
  • Outputs common Gigabit Ethernet or PCI Express® clock rates
  • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using external loop filter connection
  • Absolute pull range: ±50ppm
  • FemtoClock frequency multiplier provides low jitter, high frequency output
  • FemtoClock VCO range: 490MHz - 680MHz
  • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.421ps (typical)
  • Full 3.3V supply, or mixed 3.3V core 2.5V output supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package




Design & Development