The 5PB1216 is a high-performance TCXO / LVCMOS clock fanout buffer with individual OE pin for each output. The CLKIN pin can accept either a square wave (LVCMOS) or clipped sine wave (such as TCXO clipped sine wave output) as input.

The 5PB1216 has industry-leading low jitter and extremely low current consumption, making it ideal for smart mobile devices.

Features

  • Extremely low operating and standby current consumption
  • Low RMS Additive Phase jitter
  • 2.5 V to 3.3 V power supply voltage
  • Six outputs with individual Output Enable pin
  • One input
  • OE_OSC control pin to enable/disable reference TCXO / XO
  • Small 20-pin VFQFPN package
  • Extended temperature range (-40°C to +105°C) 

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
5PB1216NDGK
Package Info
PCB Symbol, Footprint, and 3D Model
Active VFQFPN 20 K Yes Tray
Availability

Buy / Quote
5PB1216NDGK8
Package Info
PCB Symbol, Footprint, and 3D Model
Active VFQFPN 20 K Yes Reel
Availability
Buy / Quote

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
5PB12xx Datasheet – Datasheet PDF 284 KB
Application Notes & White Papers
AN-845 Termination - LVCMOS – Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
PCNs & PDNs
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel 		– Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel 		– Product Change Notice PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
PCN# : A1711-01 Add ASECL as Alternate Assembly for Select Devices – Product Change Notice PDF 30 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location – Product Change Notice PDF 583 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Ultra-Low-Jitter Single-Ended Buffer Family Overview – Overview PDF 252 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

Type Date
An Insider’s Guide to Finding the Right Timing Device for Your System Blog Post Dec 18, 2017
Why Fanout Buffers Make More Sense Blog Post Nov 28, 2017
IDT Introduces Ultra-Low-Jitter Family of LVCMOS Clock Buffers News Mar 24, 2015