RXv2 Core Realizes Enhanced Processing Performance and Lower Power Consumption While Contributing to Higher Functionality in Embedded Systems
12 Nov 2013
TOKYO, Japan, November 12, 2013 — Renesas Electronics Corporation (TSE: 6723) today announced the development of a new, high-performance 32-bit RX CPU core, the RXv2, for embedded devices in the consumer, industrial, and office equipment fields.
The new RXv2 core features increased performance from 3.2 to 4.0 Coremark®MHz or 2.0 DMIPS/MHz, with a maximum frequency of 300MHz in 40nm. It will also feature enhanced DSP and FPU capabilities. The new core architecture will benefit applications that require a combination of higher performance, and DSP and FPU capabilities on a single MCU, such as those for factory automation, motor control, signal analysis, audio filtering, image processing, and connectivity.
The RXv2 core is backward compatible with the Renesas RXv1 CPU core employed in the existing RX family of 32-bit CISC (Complex Instruction Set Computer) microcontrollers (MCUs). The RXv2 contains all the instruction sets available in the RXv1 core, therefore applications developed for the RXv1 will be binary compatible with the new core.
The RXv1 core combined the increased processing capacity made possible by the ability of CISC MCUs to execute complex instructions with RISC (Reduced Instruction Set Computer) streamlining techniques developed for the CPUs of other Renesas MCUs. Specifically, CISC features such as variable-byte instructions are combined with RISC features such as general register machine, Harvard architecture, and five-stage pipeline. The RXv2 core leverages this architecture to deliver improved computing performance, power efficiency and high code efficiency via a dual-issue pipeline structure and Advanced Fetch Unit (AFU, Note 1).
There has been a growing demand for improved processing performance in single-chip MCUs for use in embedded devices in order to provide higher added value and accommodate increased system complexity. In particular, for motor control and mechanism control applications in the industrial and office equipment fields, there is a need for better CPU processing performance in order to achieve improved real-time performance and enhanced stability. At the same time, reducing power consumption remains an important issue. Increasing the operating frequency is a common method of boosting performance, but simply raising the frequency also increases the operating current flow and has a variety of adverse effects, such as requiring redesign of the power supply circuit or countermeasures to deal with noise on the system board. This in turn increases the overall system cost and lengthens the time needed for development. Renesas has developed the new RXv2 core to meet these demands, retaining backward compatibility with the RXv1 core, while delivering improved CPU performance and reduced power consumption.
Key features of the RXv2 core:
(1) Superior computing performance
One feature common to all RX family CPUs, including the new RXv2 core, is the floating point unit (FPU), which is essential for tasks that require numerical analysis in real time such as multimedia processing and motor control. While most CPUs incorporate a coprocessor-type FPU, the RX family of CPUs utilizes an instruction set that employs general registers for FPU operations. The FPU also features an improved pipeline processing structure and improved execution time. The number of processing cycles has been further reduced in the RXv2 by adding a DSP instruction and reducing processing cycles of the single-precision floating point, resulting in even better computing performance. The RXv2 features two dedicated 72-bit accumulators (the RXv1 has a single 64-bit accumulator) and a 1-cycle MAC instruction, enhancing the DSP function and enabling the DSP to handle even 32-bit fixed point multiply-and-accumulate operations flexibly. In addition, the RXv2 can perform DSP/FPU operations and memory accesses simultaneously, substantially boosting the signal processing capability.
When used in combination with the C compiler from IAR Systems, the RXv2 core delivers performance in excess of 4.0 Coremark®/MHz. This is equivalent to a performance increase of 25 percent (target value) over the existing RXv1 core when operating at the same frequency.
(2) Improved power efficiency
The majority of the power consumption during MCU operation stems from the paths between the CPU and the memory. For this reason, it is extremely important to optimize the memory interface when attempting to boost processor performance. In addition, if the operating speed of the memory increases, it becomes difficult to extract the maximum processing performance from the CPU due to the need to insert wait states. The architecture of the RXv2 core allows a maximum operating frequency of 300 megahertz (MHz) and includes a new AFU) that further optimizes wait states for the on-chip flash memory and enables fast branching. Typically, processors use caching to reduce wait states and alleviate the penalty that arises when branching occurs. By optimizing the AFU of the RXv2 core for the on-chip flash memory, the AFU is able to actually reduce the number of memory accesses that take place during cache operation, substantially reducing power consumption while alleviating the penalty from wait states and branching. In this way, power consumption is reduced and memory access performance improved at the same time. The new RXv2 core is based on an advanced 40 nanometer (nm) process, which contributes to a reduction in power consumption of 40 percent compared with the Renesas RXv1 core based on the 90 nm process.
(3) High code efficiency
In the embedded field, it is essential to reduce the memory area used in order to reduce costs, so Renesas RX family CPUs use a compact CISC architecture and a selective instruction set about the same size as that of RISC processors. To achieve greater efficiency with the RXv2 core, Renesas analyzed which instructions and addressing modes were used most frequently in actual applications, assigned short instruction codes to the most frequently used instructions, and adopted an efficient three-operand format. This results in code efficiency up to 30 percent higher than that of a typical RISC architecture.
RX development ecosystem
The development environment is a key component in extracting the full processing performance of the CPU, and a highly efficient C compiler is essential. With this in mind, Renesas collaborated closely with IAR Systems from the development stage of the RXv2 core, enabling IAR Systems to simultaneously release their IAR Embedded Workbench® for RX with support for the new RXv2 CPU core, enabling system designers to start development work from an early stage. IAR Embedded Workbench® for RX, an integrated development environment from IAR Systems, can realize performance exceeding 4.0 Coremark (Note 2)/MHz, allowing system designers to extract the full performance potential of the RXv2 core.
Renesas also provides a DSP library and support for C compilers, operating systems, and middleware through e² studio, Renesas' Eclipse-based integrated development environment (IDE) (Note 3). This enables system designers to minimize their investment at the initial stages of development. Renesas is also preparing an RX Software Package that bundles an evaluation board with OS, middleware and peripheral drivers to come with an MCU built around the RXv2. Renesas is also strengthening its collaboration with partner companies supplying OS and middleware. All of these efforts contribute to enhance development efficiency for customers.
Refer to the separate sheet for the main specifications of the new RXv2 core.
Renesas plans to start sample shipments of RXv2-based MCUs, as well as the RX Software Package, in the first quarter of FY2014.
(Note 1) AFU:
A cache-based instruction fetch and data access mechanism with dedicated entries for branching involving the on-chip flash memory.
(Note 2) Coremark:
A benchmark test created by the Embedded Microprocessor Benchmark Consortium (EEMBC) of the United States specifically for evaluating CPU cores. It consists of a suite of programs written in C that carry out tasks such as data reads and writes, integer operations, and control operations.
(Note 3) Eclipse:
An integrated development environment supplied by the Eclipse Foundation and that is widely used in the embedded field internationally.
About Renesas Electronics Corporation
Renesas Electronics Corporation (TSE: 6723) delivers trusted embedded design innovation with complete semiconductor solutions that enable billions of connected, intelligent devices to enhance the way people work and live. A global leader in microcontrollers, analog, power, and SoC products, Renesas provides comprehensive solutions for a broad range of automotive, industrial, home electronics, office automation, and information communication technology applications that help shape a limitless future. Learn more at renesas.com.
(Remarks) IAR Embedded Workbench is a registered trademark of IAR Systems. Other product and service names that appear in this press release are trademarks or registered trademarks of their respective owners.
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