Low Latency DRAM (dynamic random-access memory) is Renesas' large-density memory boasting high performance. Incorporating high-performance technology used in our synchronous SRAM and the pseudo-SRAM technology used in mobile-specified RAM, Low Latency DRAM is ideal for use in various networking applications. With a fast random access time-and data latency lower than other DRAM products-Low Latency DRAM realizes extremely high performance compared to commodity DRAM. Those features, combined with large density and lower cost per bit compared to SRAM solutions make Low Latency DRAM an attractive choice for use in next-generation, high-performance networking products.
Features
- Large capacity and high-speed access
- Double-data-rate architecture
- Common I/O
- PLL circuitry
- Specifications for various network markets
Related Solutions
Low Latency High Bandwidth Memory
Renesas’ low latency high bandwidth memory consists of multiple Renesas original low latency memory dies and realizes high random access rate and small data granularity as well as high bandwidth. By populating the stack memory along with your accelerator or processor in the same package, you can differentiate your systems with its performance improvement by keeping effective bandwidth high even at non-sequential memory access. The stack memory accelerates datacenter applications such as artificial intelligence (deep learning, convolutional neural network, etc.), graph analytics, database, and sparse matrix. It also fits network applications such as table lookup with high search rate, packet buffer, control memory in routers, switches etc.
Features
- Stacked Memory: The stack memory is integrated with a customer’s ASIC, GPU, CPU, NPU, FPGA, AI accelerator on a silicon interposer in the same package.
- High Random Access Rate and Small Data Granularity: 16 billion random access per second and 16-Byte data granularity realize high effective bandwidth regardless of applications.
- Guarantees Tjmax = 115 °C: Renesas’ Low Latency DRAM products have a long history to meet severe high maximum temperature requirements with long life from network industry customers. The new stack memory also guarantees Tjmax = 115 °C and delivers realistic solutions to your package thermal problem.
Lineup/Specifications
| Density (Gb) | Config. | Burst Length | Clock Freq. (MHz) | Data Width | tRC (ns) | Access Rate (Maps) | Bandwidth (Gbps) | Data Granularity | VDDQ (I/O) (V) | Status |
|---|---|---|---|---|---|---|---|---|---|---|
| 9Gb/18Gb | 1 | 2 | 1,000 | x 1,152 | 12.0 | 16,000 | 2,304 | 16 Bytes | 1.0 | 9Gb Sampling |
| 1.2 | ||||||||||
| 2 | 4 | 1,000 | x 1,152 | 16.0 | 8,000 | 2,304 | 32 Bytes | 1.0 | 9Gb Sampling | |
| 1.2 |
Related Documents
- Low Latency High Bandwidth Memory Datasheet (Digest Edition) (PDF)
- Low Latency High Bandwidth Memory Application Note (PDF)
Contact Us
For additional information, send an email inquiry to LowLatencyHBM@lm.renesas.com