Overview

Description

The 8T74S208C-01 is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T74S208C-01 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T74S208C-01 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up, all outputs are disabled.

Features

  • One differential input reference clock
  • Differential pair can accept the following differential input levels:
    LVDS, LVPECL, CML
  • Integrated input termination resistors
  • Eight LVDS outputs
  • Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
  • Maximum input clock frequency: 1GHz
  • LVCMOS interface levels for the control inputs
  • Individual output enabled/ disabled by I2C interface
  • Output skew: 45ps (maximum)
  • Output rise/fall times: 370ps (maximum)
  • Low additive phase jitter, RMS: 96fs (typical)
  • Full 2.5V supply voltage
  • Outputs disabled at power-up
  • Lead-free (RoHS 6) 32-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

Documentation

Title Type Date
PDF558 KB
Datasheet
PDF1.99 MB
Application Note
PDF170 KB
Application Note
PDF495 KB
Application Note
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Application Note
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Application Note
PDF565 KB
Application Note
PDF121 KB
Application Note
PDF217 KB
Overview
PDF1.83 MB
Overview
PDF728 KB
Product Change Notice
PDF983 KB
Product Change Notice
PDF583 KB
Product Change Notice
PDF36 KB
Product Change Notice
PDF596 KB
Product Change Notice
PDF544 KB
Product Change Notice
PDF761 KB
Product Change Notice

Design & Development

Models