Renesas Electronics Announces Development of New SRAM Circuit Technologies to Reduce Adverse Impacts of Random Variability in Scaled-down LSI Devices

Demonstrated Operation of Large-Capacity SRAM with the World's Highest Level of Bit-density at 40nm node

13 Jul 2010

TOKYO, Japan, July 13, 2010 — Renesas Electronics Corporation (TSE: 6723) today announced the successful demonstration of new SRAM circuit technologies that reduces the adverse impacts of increased random variability in advanced LSIs at the 40-nanometer (nm) node and beyond, and yet continues to address the increasing demand for smaller SRAM devices.

 

Renesas Electronics tested the prototype 2Mb (megabit) SRAM devices with the world's highest level of bit density at the 40 nm node, and successfully confirmed the basic operation of those prototypes.

 

As miniaturization of the SRAM circuits progresses, random variability has begun to make the design of advanced semiconductor devices more difficult. Among the constituent elements of such semiconductor devices, SRAM is the most susceptible to the effects of this random variability, and merely extending conventional technology results in an unacceptable diminution in the operating margin necessary to ensure stable SRAM performance. Methods such as the addition of multiple power control circuits to enable individual control of SRAM power lines, word lines, and data lines (bit lines) have been proposed. However, despite the miniaturization of the SRAM, such approaches make it difficult to reduce the overall area of devices due to the addition of large-sized power control circuits.

 

Key features of the newly developed technologies are described below.

 

  • (1) Multi-step word line control technology to reduce the degradation of operating margin

    Word line voltage control is performed in multiple steps over time, making it possible to combine the functions of the multiple power control circuits of the previous approach into control circuits for the word lines alone. Since word line voltage control is performed at a slower pace, stable SRAM read and write operation is maintained even if there is a random variability in the characteristics of the scaled-down CMOS elements. In addition, a higher bit density can be achieved since power control circuits are provided for the word lines only.

 

  • (2) Hierarchical SRAM technology for increased speed and smaller circuit area

    A newly developed hierarchical SRAM technology divides up the bit lines so that each is connected to fewer tiny SRAM cells. To these divided bit lines, signal amplifier circuits called “local sense amplifiers” (LSA) have been added, which assist the operation of the main sense amplifiers. This arrangement makes it possible to avoid a reduction in the SRAM operating speed due to the slow pace of the multi-step word line control used. In addition, the LSA are fabricated using the same ultrafine process used for the tiny SRAM cells, resulting in high bit density and minimizing any increase in the overall circuit area including the LSA and the power control circuits for the multi-step word line control.

 

Renesas Electronics used these newly developed technologies to fabricate 2Mb SRAM prototype devices at the 40 nm CMOS process node with tiny SRAM cells of 0.248 square micrometers (µm²), achieving the world's highest level of bit density of 2.98 megabits per square millimeter (Mb/mm²). The stable operation of the prototype SRAM has been verified.

 

The new technologies not only provide a countermeasure against increased random variability in CMOS device characteristics at ultrafine fabrication nodes of 40 nm and beyond, but they also have the potential to help overcome problems related to random variability in characteristics as efforts are made to further reduce power-supply voltage levels for ultra low-power applications.

 

Renesas Electronics considers the newly developed SRAM circuit technologies to be an essential technology to realizing advanced system LSIs combining reduced cost and lower power consumption, and the company plans to strengthen R&D work aimed at the early realization of products based on these technologies.

 

Renesas Electronics presented the results of this research at the 2010 Symposium on VLSI Circuits, which was held in Honolulu, Hawaii from June 16 to June 18.

 

About Renesas Electronics Corporation

Renesas Electronics Corporation (TSE: 6723) delivers trusted embedded design innovation with complete semiconductor solutions that enable billions of connected, intelligent devices to enhance the way people work and live. A global leader in microcontrollers, analog, power, and SoC products, Renesas provides comprehensive solutions for a broad range of automotive, industrial, infrastructure, and IoT applications that help shape a limitless future. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, and YouTube.


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