The evaluation kit supports electrical AC and DC measurements of the 8V19N850DNLGI, a fully integrated radio synchronizer and JESD204B/C clock jitter attenuator. The device on the board accepts any input frequency from 1Hz to 1GHz. Locked to a selected input, the device PLLs generate clock and SYSREF signals for converter reference frequency and data frame synchronization. The 8V19N850 supports two independent frequency domains: One generates transport network clocks, such as Ethernet frequencies at 4 outputs and the other one generates radio base station clocks at 12 outputs (ADC/DAC reference clocks and SYSREF signals). Each frequency domain uses a DPLL for frequency translation, clock filtering and jitter attenuation. The DPLLs provide a programmable bandwidth and a DCO function for real-time frequency/phase adjustment.


The board has SMA connectors to relevant I/O of the device:

  • 2 differential clock inputs
  • 4 differential digital outputs
  • 5 differential RF-PLL outputs
  • 5 SYSREF outputs (JESD204B/C)
  • On-board EEPROM stores startup-configuration data
  • 4 GPIO controls
  • Selectable output buffer voltage
  • XO_DPLL and OSCI terminals can use laboratory signal generator or OCXO/TCXO/XO components and board
  • Laboratory power supply connectors
  • Serial port for configuration and register read out

Kit contents:

  • 8V19N850 evaluation board
  • User’s Guide
  • Configuration software (TCP file for Timing Commander)
  • Configuration example file for four build-in device settings
  • Board schematic and BOM


タイトル language 分類 形式 サイズ 日付
star 8V19N850 Evaluation Board Manual マニュアル-開発ツール PDF 2.66 MB
8V19N850 Hardware Design Guide ガイド PDF 401 KB


タイトル language 分類 形式 サイズ 日付
Timing Commander Personality File for 8V19N850D (v3.2.0) ソフトウェア/ツール-その他 TCP 5.31 MB