特長

• Logic & Mixed Signal Circuits 
• Highly Versatile Macrocells 
• Read Back Protection (Read Lock) 
• 1.8 V (±5%) to 5 V (±10%) VDD
• 1.8 V (±5%) to 5 V (±10%) VDD2 (VDD2 ≤ VDD)
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• AEC-Q100 Grade 1

Macrocells Overview

• Four Analog Comparators (ACMP);
• Two Voltage References (Vref);
• Nineteen Combination Function Macrocells:
  • Three Selectable DFF/Latch or 2-bit LUTs;
  • One Selectable Continuous DFF/Latch or 3-bit LUT;
  • Four Selectable DFF/Latch or 3-bit LUTs;
  • One Selectable Pipe Delay or 3-bit LUT;
  • One Selectable Programmable Function Generator or 2-bit LUT;
  • Five 8-bit delays/counters or 3-bit LUTs;
  • Two 16-bit delays/counters or 4-bit LUTs;
  • Two Deglitch Filters with Edge Detectors;
• State Machine:
  • Eight States;
  • Flexible input logic from state transitions;
• Serial Communications:
  • I²C Protocol compliant;
• Pipe Delay – 16 stage/3 output (Part of Combination Function Macrocell);
• Programmable Delay;
• One Inverter;
• Two Oscillators (OSC):
  • Configurable 25 kHz/2 MHz;
  • 25MHz RC Oscillator;
• Crystal Oscillator;
• Power-On-Reset (POR);
• Eight Byte RAM + OTP User Memory:
  • RAM Memory space that is readable and writable via I²C;
  • User defined initial values transferred from OTP.

アプリケーション