The M2053 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables.

特長

  • Integrated SAW delay line
  • Output of 15 to 700 MHz *
  • Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz)
  • Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios:
  • - M2053: Map 10GbE to 66B/64B or 255/238 FEC
  • Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance
  • LVPECL clock output (CML and LVDS options available)
  • Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL
  • Loss of Lock (LOL) output pin
  • Narrow Bandwidth control input (NBW Pin)
  • Hitless Switching (HS) options with or without Phase Build-out (PBO) available
  • performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection
  • Single 3.3V power supply
  • Small 9 x 9 mm SMT (surface mount) package

製品選択

This device is factory-configurable. Try the Custom Part Configuration Utility.
製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete CLCC 36 C はい Tube
Availability
Obsolete CLCC 36 C はい Reel
Availability

ドキュメント&ダウンロード

タイトル language 分類 形式 サイズ 日付
PCN / PDN
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 製品変更通知 PDF 361 KB
PDN# : Z-13-01 PRODUCT DISCONTINUANCE NOTICE 製品中止通知 PDF 71 KB