概要

Dual DDR zero delay buffer

  • High performance, low jitter zero delay buffer
  • I2C for functional and output control
  • Dual bank 1-6 differential clock distribution
  • 2 separate feedback in & out for input to output
  • Synchronization for each bank
  • Supports up to 4 DDR DIMMs
  • Supports up to 533MHz (DDRII 1066)

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9P946AFLF
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Tube
    9P946AFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 48 C Yes Reel
    Parametric Table tips

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