概要
説明
The CD40174BMS consists of six identical D-Type flip-flops having independent data inputs. The clock and clear inputs are common to all six units. Data is transferred to the Q outputs on the positive-going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input. The CD40174BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T, Frit Seal DIP H1E and Ceramic Flatpack H6W.
特長
- High-voltage type (20V rating)
- 5V, 10V and 15V parametric ratings
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20V
- Maximum input current of 1µA at 18V over full package temperature range, 100nA at 18V and +25 °C
- Noise margin (over full package temperature range): 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
- Meets all requirements of JEDEC tentative standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
アプリケーション
アプリケーション
- Shift registers
- Buffer/Storage registers
- Pattern generators
ドキュメント
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日付 | |
|---|---|---|
| PDF 323 KB | データシート | |
| PDF 467 KB | カタログ | |
| PDF 4.85 MB | カタログ | |
| PDF 360 KB | Price Increase Notice | |
| その他資料 | ||
| PDF 533 KB | ホワイトペーパー | |
| PDF 499 KB | Product Advisory | |
| PDF 230 KB | 製品変更通知 | |
| PDF 338 KB | アプリケーションノート | |
9 items
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設計・開発
モデル
ECADモデル
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Processing table
| SBDIP | Tube | 25 | 5962R9660501VEC | ||
| CFP | Tray | 25 | 5962R9660501VXC |
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